1. Field of the Invention
The present invention relates to a chip-enable-signal generation circuit usable for both a device having m chips at maximum and a device having 2.sup.m chips at maximum or usable for both a device having m chips at maximum and a device having 2.sup.m+n chips at maximum, and, also, relates to a memory device designed to have such a chip-enable-signal generation circuit implemented thereon. The present invention particularly relates to a chip-enable-signal generation circuit which can generate an appropriate chip-enable signal even if chip information is not supplied externally, and relates to a memory device designed to have such a chip-enable-signal generation circuit implemented thereon.
Flash memories have been making a progress in the market. Flash memories are EEPROMs having a function to erase the memory contents at once. Since flash memories can be made small with high circuit density, their applications to various electronics equipment are anticipated.
Because of the wide range of applications, memory cards having flash memories therein are expected to be provided in a variety of product types, ranging from one having several flash memories to one having several dozens of flash memories in accordance with the types of electronics equipment to which they are applied. It is difficult, however, to provide different types of controllers for different types of memory cards according to the number of flash memories. It is necessary to cope with this situation without increasing the number of terminals, for example.
2. Description of the Related Art
Methods of generating a chip-enable signal supplied to flash memory chips or the like include generating a chip-enable signal by allocating the chip-enable signal directly to each bit of a binary code, or generating a chip-enable signal by decoding a binary code.
When generating a chip-enable signal for m chips, for example, the former method allocates a chip-enable signal to each bit of a m-bit binary code so as to indicate an enable status of a selected one of the m chips.
When a first one of four chips is to be enabled, for example, a chip-enable signal [0001] is generated. When the second chip is to be enabled, a chip-enable signal [0010] is generated. By the same token, a chip-enable signal [0100] is generated in order to enable the third chip. Finally, a chip-enable signal [1000] enables the fourth chip.
When generating a chip-enable signal for 2.sup.m chips, the latter method decodes a m-bit binary codes, and generates a chip-enable signal indicative of an enable status of a selected chip.
In order to enable a first one of 16 chips, for example, a binary code [0001] is decoded to generate a chip-enable signal [0000000000000001]. When the second chip is to be enabled, a binary code [0010] is decoded to generate a chip-enable signal [0000000000000010]. Further, a binary code [0011] is decoded to generate a chip-enable signal [0000000000000100], which is to enable the third chip.
The former method generates a chip-enable signal for m chips by using a m-bit code, so that this method is typically used when the number of chips is relatively small. The latter method generates a chip-enable signal for 2.sup.m chips by using a m-bit code, so that this method is typically used when the number of chip is relatively large.
When there is a need to supply a chip-enable signal to flash memory chips or the like, a controller for generating the chip-enable signal usually generates the chip-enable signal based on the former method in the case of a small number of chips, and generates the chip-enable signal based on the latter method in the case of a large number of chips.
In order to make a single controller usable for both a device having a small number of chips and a device having a large number of chips, the controller needs to be informed whether it is implemented on the device having a small number of chips or on the device having a large number of chips In this manner, the controller can select an appropriate method of generating a signal.
In order to achieve this, a related-art controller is provided with a dedicated terminal for signal exchange. This dedicated terminal is used for informing the controller of the number of chips or an appropriate method of generating a chip-enable signal.
In such a configuration, the controller already having many terminals for signal exchanges with external sources needs to have an extra terminal dedicated for this purpose.
An increase in the number of terminals hinders an effort to miniaturize a controller size. Use of the configuration described above results in the miniaturization of a controller device being undermined.
Devices having flash memories implemented thereon are typically expected to be provided in a small size by utilizing a relatively small size of the flash memories. The configuration of the related art, therefore, goes against this expectation for miniaturization.
Accordingly, there is a need for a chip-enable-signal generation circuit which is usable for both a device having m chips at maximum and a device having 2.sup.m chips at maximum or usable for both a device having m chips at maximum and a device having 2.sup.m+n chips at maximum, and can generate an appropriate chip-enable signal without requiring external help to obtain information about chips on the device, and, also, there is a need for a memory device suitable for having such a chip-enable-signal generation circuit implemented thereon.